Analysis of Inductive Effects of On-chip and On-board Return Current Path for Performance Degradation Modeling in VLSI design

Vol.4 No.3

Year: 2010

Issue: January - March

Title: Analysis of Inductive Effects of On-chip and On-board Return Current Path for Performance Degradation Modeling in VLSI design   

Author Name: Sourabh Sthapak, Jeffrey Fan   

Synopsis:   

As the dimension of interconnects in Integrated circuits has become dominant, the inductive effects of the wires cannot be ignored anymore. At high frequency, the return current distributes itself close to the signal path and any increase in the inductance of the return path hampers signal integrity. The multi-layered power distribution network (PDN) is stressed when many devices draw current simultaneously, creating noise in the supply rails. This high speed current not only causes ground bounce and power supply sag but it also needs a low inductance return path. Since high frequency involved in contemporary signaling makes the interconnects to behave as lossy transmission lines, the chip may sustain less noise margin due to environmental or process variations. If the inductive effort is considered, the design will be more robust and variability-free, thus improving the defect tolerance. In this paper, a SPICE based analysis of “on-board” high speed return current path is conducted and techniques and results are then extended for “on-chip” return current path analysis. In addition to avoiding operational failures, a priori knowledge of signal and its respective return path would greatly help to simplify interconnect designing and routing.