An Exclusion and Equivalence Algorithm for Reduction of Bus Transitions in Low Power VLSI

Vol.2 No.3

Year: 2008

Issue: January-March

Title: An Exclusion and Equivalence Algorithm for Reduction of Bus Transitions in Low Power VLSI   

Author Name: Padma Priya K, Paradesi Rao D. V   

Synopsis:    

The power consumption is one of the most important design criteria in on-chip bus design. In VLSI design using deep sub micron technology, the bus energy reduction has become more and more important. As technology is scaling down, the increased interconnect wire aspect ratio and the reduced spacing between the individual wires within the bus result in increased cross coupling capacitances. They also increase cross talk noise and power dissipation in the data buses. In addition there is also a self-capacitance introduced between two adjacent data lines. We have developed an encoding algorithm that reduces the coupling transitions (1 to 0 or 0 to 1 state transition) and also the self-transitions in the data buses to minimize the energy dissipation. The technique requires 2 extra bits for sending coding information regardless of the bit width of the bus and does not assume anything about the nature of the data.