A Technique to Reduce Data-Bus Coupling Transitions in DSM Technology

Vol.4 No.2

Year: 2009

Issue: October - December

Title: A Technique to Reduce Data-Bus Coupling Transitions in DSM Technology   

Author Name: Sathish A, M. Madhavi Latha , K. Lal Kishore , M.V. Subramanyam , C.S. Reddy   

Synopsis:   

With growing integration density and shrinking feature size in the deep sub-micrometer (DSM) technologies, on-chip buses plays an important role in overall performance of the system. Due to a large buses and deep sub-micron effects where coupling capacitance between bus lines are in the same order of magnitude as base capacitance, power consumption of interconnects starts to have a significant impact on a system’s total power consumption. In many digital processors, the power dissipation on the buses is a major part of the total chip power dissipation. For CMOS circuits most power is dissipated as a dynamic power for charging and discharging node capacitances. Coupling transitions contribute to significant energy loss in deep sub-micron data buses. Earlier schemes using the switching activity are not valid in these buses which takes account only substrate capacitance. Hence a new low coupling transition bus encoding scheme is proposed which can reduce the power consumption in   on-chip data buses by reducing the coupling transitions. The proposed technique can able to reduce the coupling transition by 41% to 44% and its efficiency is 1% to 18% more compare with others encoding techniques.